Knowledge Center

PUBLICATIONS

Conference papers, journal articles, and white papers from the Cogita EDA team on verification analytics, AI/ML methodology, and semiconductor debug.

DVCON US

RTL Performance Isn’t Just a Number - It’s a Story

Checking ASIC performance differs from functional verification: it’s not only about correct outputs but also whether they arrive fast enough, within resource limits, and at expected throughput. Standard performance metrics include latency, throughput, bandwidth, and resource utilization. Best practices treat performance as a firstclass metric: define goals, monitor, cover, assert, and link to functional checks. However, identifying the root cause of performance issues remains challenging.

March 2, 2026

DVCON Europe

Harnessing the Strength of Statistics and Visualization in Verification

This paper explores how statistics and visualization, which remain largely unexploited today, can improve verification processes. Verification debug is data-intensive, and the biggest challenge for engineers is to grasp enormous amounts of data from different simulation outputs.

October 15, 2024

DVCON US

Efficient application of AI algorithms for large-scale verification environments based on NoC architecture

The growing complexity of SoCs is challenging the efficiency of present-day verification approaches, making verification processes increasingly more involved. As waveform databases expand in size and simulation run-time becomes more time consuming, logs and code execution traces are harder to read and understand. This requires greater resourcefulness from verification teams, alongside more powerful verification tools.

March 5, 2024

DVCON Europe

A perfect blend of verification techniques, platforms, and AI-empowered debugging in Ethernet Subsystem Verification

The verification of SoC hardware and software can present numerous challenges, with engineers dealing with the need to balance fast verification results and the inherent complexity of the system. This paper gives an overview of the flow that is followed in the SoC verification of the Ethernet Subsystem.‍

November 14, 2023

SemiEngineering

Debug: The Schedule Killer

Debug often takes a large portion of the chip development and can significantly disrupt schedules. How can we make debug more predictable and faster? Vtool’s Cogita provides “an approach that combines machine learning with advanced visualization, and an all-inclusive debug methodology, that has been proven to reduce the debug cycle dramatically”, said Hagai Arbel, Vtool CEO. Read all about ‘Debug: The Schedule Killer’ in this Semiconductor Engineering article by Brian Bailey. ‍

June 30, 2021